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<title>VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit Granularity </title></head>
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<h1>VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit Granularity</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F3A.W0 23 /r ib</p>
<p>VSHUFF32X4 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Shuffle 128-bit packed single-precision floating-point values selected by imm8 from ymm2 and ymm3/m256/m32bcst and place results in ymm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F3A.W0 23 /r ib</p>
<p>VSHUFF32x4 zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Shuffle 128-bit packed single-precision floating-point values selected by imm8 from zmm2 and zmm3/m512/m32bcst and place results in zmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F3A.W1 23 /r ib</p>
<p>VSHUFF64X2 ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Shuffle 128-bit packed double-precision floating-point values selected by imm8 from ymm2 and ymm3/m256/m64bcst and place results in ymm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F3A.W1 23 /r ib</p>
<p>VSHUFF64x2 zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Shuffle 128-bit packed double-precision floating-point values selected by imm8 from zmm2 and zmm3/m512/m64bcst and place results in zmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F3A.W0 43 /r ib</p>
<p>VSHUFI32X4 ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Shuffle 128-bit packed double-word values selected by imm8 from ymm2 and ymm3/m256/m32bcst and place results in ymm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F3A.W0 43 /r ib</p>
<p>VSHUFI32x4 zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Shuffle 128-bit packed double-word values selected by imm8 from zmm2 and zmm3/m512/m32bcst and place results in zmm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F3A.W1 43 /r ib</p>
<p>VSHUFI64X2 ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Shuffle 128-bit packed quad-word values selected by imm8 from ymm2 and ymm3/m256/m64bcst and place results in ymm1 subject to writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F3A.W1 43 /r ib</p>
<p>VSHUFI64x2 zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Shuffle 128-bit packed quad-word values selected by imm8 from zmm2 and zmm3/m512/m64bcst and place results in zmm1 subject to writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>256-bit Version: Moves one of the two 128-bit packed single-precision floating-point values from the first source operand (second operand) into the low 128-bit of the destination operand (first operand); moves one of the two packed 128-bit floating-point values from the second source operand (third operand) into the high 128-bit of the destination operand. The selector operand (third operand) determines which values are moved to the destination operand.</p>
<p>512-bit Version: Moves two of the four 128-bit packed single-precision floating-point values from the first source operand (second operand) into the low 256-bit of each double qword of the destination operand (first operand); moves two of the four packed 128-bit floating-point values from the second source operand (third operand) into the high 256-bit of the destination operand. The selector operand (third operand) determines which values are moved to the destination operand.</p>
<p>The first source operand is a vector register. The second source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a vector register.</p>
<p>The writemask updates the destination operand with the granularity of 32/64-bit data elements.</p>
<p><strong>Operation</strong></p>
<p>Select2(SRC, control) {</p>
<p>CASE (control[0]) OF</p>
<p>0:</p>
<p>TMP (cid:197) SRC[127:0];</p>
<p>1:</p>
<p>TMP (cid:197) SRC[255:128];</p>
<p>ESAC;</p>
<p>RETURN TMP</p>
<p>}</p>
<p>Select4(SRC, control) {</p>
<p>CASE (control[1:0]) OF</p>
<p>0:</p>
<p>TMP (cid:197) SRC[127:0];</p>
<p>1:</p>
<p>TMP (cid:197) SRC[255:128];</p>
<p>2:</p>
<p>TMP (cid:197) SRC[383:256];</p>
<p>3:</p>
<p>TMP (cid:197) SRC[511:384];</p>
<p>ESAC;</p>
<p>RETURN TMP</p>
<p>}</p>
<p><strong>VSHUFF32x4 (EVEX versions)</strong></p>
<p>(KL, VL) = (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF (EVEX.b = 1) AND (SRC2 *is memory*)</p>
<p>THEN TMP_SRC2[i+31:i] (cid:197) SRC2[31:0]</p>
<p>ELSE TMP_SRC2[i+31:i] (cid:197) SRC2[i+31:i]</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>IF VL = 256</p>
<p>TMP_DEST[127:0] (cid:197) Select2(SRC1[255:0], imm8[0]);</p>
<p>TMP_DEST[255:128] (cid:197) Select2(SRC2[255:0], imm8[1]);</p>
<p>FI;</p>
<p>IF VL = 512</p>
<p>TMP_DEST[127:0] (cid:197) Select4(SRC1[511:0], imm8[1:0]);</p>
<p>TMP_DEST[255:128] (cid:197) Select4(SRC1[511:0], imm8[3:2]);</p>
<p>TMP_DEST[383:256] (cid:197) Select4(TMP_SRC2[511:0], imm8[5:4]);</p>
<p>TMP_DEST[511:384] (cid:197) Select4(TMP_SRC2[511:0], imm8[7:6]);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+31:i] (cid:197) TMP_DEST[i+31:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>THEN DEST[i+31:i] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VSHUFF64x2 (EVEX 512-bit version)</strong></p>
<p>(KL, VL) = (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF (EVEX.b = 1) AND (SRC2 *is memory*)</p>
<p>THEN TMP_SRC2[i+63:i] (cid:197) SRC2[63:0]</p>
<p>ELSE TMP_SRC2[i+63:i] (cid:197) SRC2[i+63:i]</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>IF VL = 256</p>
<p>TMP_DEST[127:0] (cid:197) Select2(SRC1[255:0], imm8[0]);</p>
<p>TMP_DEST[255:128] (cid:197) Select2(SRC2[255:0], imm8[1]);</p>
<p>FI;</p>
<p>IF VL = 512</p>
<p>TMP_DEST[127:0] (cid:197) Select4(SRC1[511:0], imm8[1:0]);</p>
<p>TMP_DEST[255:128] (cid:197) Select4(SRC1[511:0], imm8[3:2]);</p>
<p>TMP_DEST[383:256] (cid:197) Select4(TMP_SRC2[511:0], imm8[5:4]);</p>
<p>TMP_DEST[511:384] (cid:197) Select4(TMP_SRC2[511:0], imm8[7:6]);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197) TMP_DEST[i+63:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>THEN DEST[i+63:i] (cid:197)(cid:3)0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VSHUFI32x4 (EVEX 512-bit version)</strong></p>
<p>(KL, VL) = (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF (EVEX.b = 1) AND (SRC2 *is memory*)</p>
<p>THEN TMP_SRC2[i+31:i] (cid:197) SRC2[31:0]</p>
<p>ELSE TMP_SRC2[i+31:i] (cid:197) SRC2[i+31:i]</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>IF VL = 256</p>
<p>TMP_DEST[127:0] (cid:197) Select2(SRC1[255:0], imm8[0]);</p>
<p>TMP_DEST[255:128] (cid:197) Select2(SRC2[255:0], imm8[1]);</p>
<p>FI;</p>
<p>IF VL = 512</p>
<p>TMP_DEST[127:0] (cid:197) Select4(SRC1[511:0], imm8[1:0]);</p>
<p>TMP_DEST[255:128] (cid:197) Select4(SRC1[511:0], imm8[3:2]);</p>
<p>TMP_DEST[383:256] (cid:197) Select4(TMP_SRC2[511:0], imm8[5:4]);</p>
<p>TMP_DEST[511:384] (cid:197) Select4(TMP_SRC2[511:0], imm8[7:6]);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+31:i] (cid:197) TMP_DEST[i+31:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>THEN DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VSHUFI64x2 (EVEX 512-bit version)</strong></p>
<p>(KL, VL) = (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF (EVEX.b = 1) AND (SRC2 *is memory*)</p>
<p>THEN TMP_SRC2[i+63:i] (cid:197) SRC2[63:0]</p>
<p>ELSE TMP_SRC2[i+63:i] (cid:197) SRC2[i+63:i]</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>IF VL = 256</p>
<p>TMP_DEST[127:0] (cid:197) Select2(SRC1[255:0], imm8[0]);</p>
<p>TMP_DEST[255:128] (cid:197) Select2(SRC2[255:0], imm8[1]);</p>
<p>FI;</p>
<p>IF VL = 512</p>
<p>TMP_DEST[127:0] (cid:197) Select4(SRC1[511:0], imm8[1:0]);</p>
<p>TMP_DEST[255:128] (cid:197) Select4(SRC1[511:0], imm8[3:2]);</p>
<p>TMP_DEST[383:256] (cid:197) Select4(TMP_SRC2[511:0], imm8[5:4]);</p>
<p>TMP_DEST[511:384] (cid:197) Select4(TMP_SRC2[511:0], imm8[7:6]);</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197) TMP_DEST[i+63:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>THEN DEST[i+63:i] (cid:197)(cid:3)0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VSHUFI32x4 __m512i _mm512_shuffle_i32x4(__m512i a, __m512i b, int imm);</p>
<p>VSHUFI32x4 __m512i _mm512_mask_shuffle_i32x4(__m512i s, __mmask16 k, __m512i a, __m512i b, int imm);</p>
<p>VSHUFI32x4 __m512i _mm512_maskz_shuffle_i32x4( __mmask16 k, __m512i a, __m512i b, int imm);</p>
<p>VSHUFI32x4 __m256i _mm256_shuffle_i32x4(__m256i a, __m256i b, int imm);</p>
<p>VSHUFI32x4 __m256i _mm256_mask_shuffle_i32x4(__m256i s, __mmask8 k, __m256i a, __m256i b, int imm);</p>
<p>VSHUFI32x4 __m256i _mm256_maskz_shuffle_i32x4( __mmask8 k, __m256i a, __m256i b, int imm);</p>
<p>VSHUFF32x4 __m512 _mm512_shuffle_f32x4(__m512 a, __m512 b, int imm);</p>
<p>VSHUFF32x4 __m512 _mm512_mask_shuffle_f32x4(__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);</p>
<p>VSHUFF32x4 __m512 _mm512_maskz_shuffle_f32x4( __mmask16 k, __m512 a, __m512 b, int imm);</p>
<p>VSHUFI64x2 __m512i _mm512_shuffle_i64x2(__m512i a, __m512i b, int imm);</p>
<p>VSHUFI64x2 __m512i _mm512_mask_shuffle_i64x2(__m512i s, __mmask8 k, __m512i b, __m512i b, int imm);</p>
<p>VSHUFI64x2 __m512i _mm512_maskz_shuffle_i64x2( __mmask8 k, __m512i a, __m512i b, int imm);</p>
<p>VSHUFF64x2 __m512d _mm512_shuffle_f64x2(__m512d a, __m512d b, int imm);</p>
<p>VSHUFF64x2 __m512d _mm512_mask_shuffle_f64x2(__m512d s, __mmask8 k, __m512d a, __m512d b, int imm);</p>
<p>VSHUFF64x2 __m512d _mm512_maskz_shuffle_f64x2( __mmask8 k, __m512d a, __m512d b, int imm);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>See Exceptions Type E4NF.</p>
<table>
<tr>
<td>#UD</td>
<td>If EVEX.L’L = 0 for VSHUFF32x4/VSHUFF64x2.</td></tr></table></body></html>